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Espressif Systems /ESP32-H2 /PCR /MSPI_CONF

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Interpret as MSPI_CONF

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (MSPI_CLK_EN)MSPI_CLK_EN 0 (MSPI_RST_EN)MSPI_RST_EN 0 (MSPI_PLL_CLK_EN)MSPI_PLL_CLK_EN 0MSPI_CLK_SEL 0 (MSPI_READY)MSPI_READY

Description

MSPI configuration register

Fields

MSPI_CLK_EN

Set 1 to enable mspi clock, include mspi pll clock
MSPI_RST_EN

Set 0 to reset mspi module
MSPI_PLL_CLK_EN

Set 1 to enable mspi pll clock
MSPI_CLK_SEL

set this field to select clock-source.
MSPI_READY

Query this field after reset mspi module

Links

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Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data